The controller enters the Fatal Error state when it detects an internal inconsistency. Although very unlikely, it is possible for the controller to halt operations due to soft errors that affect the controller-related configuration memory or the controller design state elements. The Fatal Error state can be indicated by the assertion of all seven state bits on the Status Interface, and potentially with a fatal error report message (HLT). This condition is non-recoverable and the FPGA must be reconfigured.