Features - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
Release Date
3.1 English

The SEM controller is device dependent and includes the following features:

  • Six IP modes to align with your SEU mitigation goals:
    • Mitigation and Testing
    • Mitigation only
    • Detect and Testing
    • Detect only
    • Emulation
    • Monitoring only
  • Features specific to mitigation modes:
    • Integration of silicon features to leverage built-in error detection capability for mitigation modes.
    • Implementation of error correction capability to support correction of soft errors.
    • ECC algorithm-based correction that supports correction of configuration memory frames with up to 4-bit errors.
    • Minimal latency in detecting and correcting multi-bit errors due to a single SEU event that is spread across adjacent frames.
    • Implementation of error classification capability to determine if corrected errors have affected configuration memory in locations essential to the function of the design.
    • Provision for error injection to support verification of the controller and evaluation of applications of the controller.
    • Provision to command the SEM controller to perform Detect only monitoring of soft errors. In this state, the SEM controller continuously monitors the configuration memory until it detects an error. After an error is detected, the SEM controller reports the error and goes to the Idle state. This command does not include error correction.
  • Variety of debug and test features during Idle:
    • Configuration frame reads (Query command).
    • Configuration register reads (Peek command).
    • Frame address translation (Translate command) translates the configuration of the Physical Frame Address (PFA) to the Linear Frame Address (LFA) and vice-versa.
    • External SPI flash memory reads (Xmem command) available when Error Classification feature is enabled.
  • Option to continuously monitor and report errors without performing error correction (Detect modes and Detect only command). In this state, the SEM controller transitions to Idle state when it detects and reports the first error it encounters.
  • Provision to command the SEM controller to perform a Diagnostic Scan. In this state, the SEM controller performs a single scan of the configuration memory and reports all detected ECC errors. After completing a single pass of the configuration memory, the SEM controller returns to the Idle state. The error detection mechanism used in this feature does not leverage the built-in error detection capability of the device. Error correction is not performed in this type of scan.
  • SPI flash master helper block provides an interface between the controller and external storage. This is required when the controller is configured to perform error classification.
  • UART helper block provides an interface between the controller and an external processor for ease of use when logging the controller status and performing error injection.
  • Flexibility to control the location of the helper blocks and configuration primitives to be in the IP boundary or example design.
  • ICAP arbitration interface to ease sharing of ICAP with other blocks and enable safe hand-off.

The following table summarizes the features of each of the modes.

Table 1. Mode Features
Features Modes
Mitigation and Testing Mitigation Only Detect and Testing Detect Only Emulation Monitoring
IP state after initialization OBSV OBSV DETECT DETECT IDLE IDLE
Correction (Repair) Yes Yes N/A N/A N/A N/A
Classification Optional Optional N/A N/A N/A N/A
Error injection Yes N/A Yes N/A Yes N/A

Debugging features:

  • Transition to Idle state
  • Configuration frames and register reads
  • External memory reads
  • Address translations
Yes Yes Yes Yes Yes Yes

On-demand detect features:

  • Detect only
  • Diagnostic scan
Yes Yes Yes Yes Yes Yes

The following table lists all the supported devices and the maximum number of configuration frames it scans, which is also equivalent to the maximum number of linear frames that is reported by the Status command (MF {8-digit hex value}).

Table 2. Maximum Number of Configuration Frames
Device MF (Dec) MF (Hex)
UltraScale XCKU035 26179 00006643
XCKU040 26179 00006643
XCKU060 37651 00009313
XCKU085 37651 00009313
XCKU095 54559 0000D51F
XCKU115 37651 00009313
XCVU065 37706 0000934A
XCVU080 54559 0000D51F
XCVU095 54559 0000D51F
XCVU125 37706 0000934A
XCVU160 37706 0000934A
XCVU190 37706 0000934A
XCVU440 78555 000132DB
UltraScale+ XCZU1EG 5684 00001634
XCZU1CG 5684 00001634
XQZU55DR 40794 00009F5A
XQZU57DR 40794 00009F5A
XQZU65DR 40794 00009F5A
XQZU67DR 40794 00009F5A
XCKU15P 75283 00012613
XCVU3P 56601 0000DD19
XCVU5P 56601 0000DD19
XCVU7P 56601 0000DD19
XCVU9P 56601 0000DD19
XCVU11P 61963 0000F20B
XCVU13P 61963 0000F20B
XCVU27P 61963 0000F20B
XCVU29P 61963 0000F20B
XCVU31P 61929 0000F1E9
XCVU33P 61929 0000F1E9
XCVU35P (SLR0) 61929 0000F1E9
XCVU35P (SLR1) 61963 0000F20B
XCVU37P (SLR0) 61929 0000F1E9
XCVU37P (SLR1 and SLR2) 61963 0000F20B
XCVU45P (SLR0) 61929 0000F1E9
XCVU45P (SLR1) 61963 0000F20B
XCVU47P (SLR0) 61929 0000F1E9
XCVU47P (SLR1 and SLR2) 61963 0000F20B
XCZU1 10373 00002885
XCZU2 10373 00002885
XCZU3 10373 00002885
XCZU4 17907 000045F3
XCZU5 17907 000045F3
XCZU6 48054 0000BBB6
XCZU7 44273 0000ACF1
XCZU9 48054 0000BBB6
XCZU11 49127 0000BFE7
XCZU15 57532 0000E0BC



XCZU17 75283 00012613
XCZU29DR 68119 00010A17
XCZU46DR 68119 00010A17
XCZU47DR 68119 00010A17
XCZU48DR 68119 00010A17
XCZU49DR 68119 00010A17
U55N (SLR1) 61963 0000F20B
U55N (SLR0) 61929 0000F1E9
U55C (SLR1 and SLR2) 61963 0000F20B
U55C (SLR0) 61929 0000F1E9
XCVU57P (SLR1 and SLR2) 61963 0000F20B
XCVU57P (SLR0) 61929 0000F1E9
XCVU19P 122412 0001DE2C
XCVU15P 122412 0001DE2C
XCVU23P 130547 0001FDF3
XCKU19P 130547 0001FDF3
XCK26 17907 000045F3
XCUX35 130547 0001FDF3
XCAU25P 31287 00007A37
XCAU20P 31287 00007A37
XCAU15P 31287 00007A37
XCAU10P 31287 00007A37