Features - 3.1 English

The SEM controller is device dependent and includes the following features:

• Six IP modes to align with your SEU mitigation goals:
  • Mitigation and Testing
  • Mitigation only
  • Detect and Testing
  • Detect only
  • Emulation
  • Monitoring only
• Features specific to mitigation modes:
  • Integration of silicon features to leverage built-in error detection capability for mitigation modes.
  • Implementation of error correction capability to support correction of soft errors.
  • ECC algorithm-based correction that supports correction of configuration memory frames with up to 4-bit errors.
  • Minimal latency in detecting and correcting multi-bit errors due to a single SEU event that is spread across adjacent frames.
  • Implementation of error classification capability to determine if corrected errors have affected configuration memory in locations essential to the function of the design.
  • Provision for error injection to support verification of the controller and evaluation of applications of the controller.
  • Provision to command the SEM controller to perform Detect only monitoring of soft errors. In this state, the SEM controller continuously monitors the configuration memory until it detects an error. After an error is detected, the SEM controller reports the error and goes to the Idle state. This command does not include error correction.
• Variety of debug and test features during Idle:
  • Configuration frame reads (Query command).
    Recommended: AMD recommends reading configuration frame before and after error injection to filter out mask bits and set expectations of IP behavior.
  • Configuration register reads (Peek command).
  • Frame address translation (Translate command) translates the configuration of the Physical Frame Address (PFA) to the Linear Frame Address (LFA) and vice-versa.
  • External SPI flash memory reads (Xmem command) available when Error Classification feature is enabled.
• Option to continuously monitor and report errors without performing error correction (Detect modes and Detect only command). In this state, the SEM controller transitions to Idle state when it detects and reports the first error it encounters.
• Provision to command the SEM controller to perform a Diagnostic Scan. In this state, the SEM controller performs a single scan of the configuration memory and reports all detected ECC errors. After completing a single pass of the configuration memory, the SEM controller returns to the Idle state. The error detection mechanism used in this feature does not leverage the built-in error detection capability of the device. Error correction is not performed in this type of scan.
• SPI flash master helper block provides an interface between the controller and external storage. This is required when the controller is configured to perform error classification.
• UART helper block provides an interface between the controller and an external processor for ease of use when logging the controller status and performing error injection.
• Flexibility to control the location of the helper blocks and configuration primitives to be in the IP boundary or example design.
• ICAP arbitration interface to ease sharing of ICAP with other blocks and enable safe hand-off.

The following table summarizes the features of each of the modes.

The following table lists all the supported devices and the maximum number of configuration frames it scans, which is also equivalent to the maximum number of linear frames that is reported by the Status command (MF {8-digit hex value}).