The Fetch Interface provides a mechanism for the controller to request data from an external source. This interface is only present when the error classification feature is enabled. See Fetch Interface for the port list and definition of this interface.
Per the description in Fetch Interface, the fetch_tbladdr input is used to specify the starting address of the controller data
table in the external memory source. See the following figure for a visual explanation.
The controller expects that the lowest 31 bits of the
fetch_tbladdr (TB) address to contain the classification base
(CB0 ) pointer to the address that contain the first byte of the essential bits
data for SLR0. If the targeted device is a multi-SLR device, the following 32 bits of the
fetch_tbladdr contain the classification base (CB1 ) pointer to
the address that contains the first byte of the essential bits data for SLR1, and so forth. If
this is a monolithic device, only one classification base pointer is required.
The ability to define fetch_tbladdr (TB) and
the classification base pointer (CBn ) enables you to use the SPI flash memory to
store other data and organize the content of the memory as they need to.
To verify that correct TB and CB values are used by the controller, these values are echoed as part of the status report that can be performed through the Monitor Interface. See Status Report.
the delivered makedata.tcl script (generates
SPI flash programming file) assumes the fetch_tbladdr value is zero and needs
to be modified if the TB and CB values needs to be customized. Ultimately, it is your
responsibility to define and organize the data that the SEM controller requires (the
classification base pointer and the essential bits data) to the appropriate address space if
the TB and CB values are changed.
As a convenience, the system-level example design provides an example SPI flash master helper block to connect to the Fetch Interface to retrieve the data from an external SPI flash. The following section discusses the behavior of the SPI flash master helper block in the SPI Interface.
If an interface other than SPI Interface is needed, the SPI flash master helper block can be replace with an alternate function. For example, the SPI flash master helper block could be replaced with a parallel flash memory controller or other scheme for inter-process communication. To enable this customization, a detailed description of the Fetch Interface signaling is available in Fetch Interface Signaling and Protocol.