Generating Bitstream - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2023-11-08
Version
3.1 English

When the supported evaluation boards are targeted, the IP configuration, generated system-level example design and constraints are configured by default to be compatible with the targeted device and platform. To generate a bitstream, follow these steps:

  1. Create a new AMD Vivado™ RTL project and choose one of the supported boards:
  2. Find the UltraScale Soft Error Mitigation IP in the Vivado IP catalog and generate the core. You do not need to modify any of the parameters because the defaults are set to the targeted platform.
  3. Generation of the IP completes after the Out-of-Context Module Runs finishes. Select the generated IP and select Open IP Example Design.
  4. Next, synthesize, implement, and generate the bitstream for the example design. This bitstream is used to program the device on the evaluation platform.