Hardware and Software Setup - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller (PG187)

Document ID
PG187
Release Date
2021-10-27
Version
3.1 English

After a bitstream is generated, connect the Platform USB (or Digilent ® ) cable and USB UART cable to the computer and board. Ensure that the cables are connected by opening up the Devices and Printers list in the Control Panel and confirm the following:

Silicon Labs CP210x USB to UART Bridge

Xilinx (this refers to the platform USB cable)

To issue commands and receive status information from UART Interface of the SEM controller, a terminal emulator program (for example, Teraterm) that supports serial port connection needs to be used and configured. For more information on how to configure the terminal emulator program, see Switching Behavior .

After programming the bitstream and debug_nets.ltx file for the VIO cores, add the hw_vio_* windows into the Hardware Manager to view and also manipulate the SEM signals.

Figure C-5: SEM Controller Hardware Manager Window

X-Ref Target - Figure C-5

X16179-sem-hw-manager-win.jpg