Placement Constraints - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2023-11-08
Version
3.1 English

The following constraints in the XDC implement a Pblock to place portions of the system-level design example into a bounded region of the selected device. The instances included in the Pblock depend on the options set at generation. The range values vary depending on device selection.

The Pblock forces packing of the soft error mitigation logic into an area physically adjacent to the ICAP site in the device. Most importantly, this maintains reproducibility in timing results. It also improves resource usage; the Pblock forces tighter packing.

The delivered Pblock is provided as an example. You are encouraged to further tighten the size of the Pblock to improve the resource usage and reduce physical footprint of the SEM controller.

create_pblock sem
resize_pblock [get_pblocks sem] -add {SLICE_X82Y75:SLICE_X87Y89}
resize_pblock [get_pblocks sem] -add {RAMB36_X8Y14:RAMB36_X8Y17}
resize_pblock [get_pblocks sem] -add {DSP48E2_X15Y30:DSP48E2_X15Y35}
add_cells_to_pblock -pblock sem -cells [get_cells example_support_wrapper/example_support/example_spi/*]
add_cells_to_pblock -pblock sem -cells [get_cells example_support_wrapper/example_support/example_uart/*]
add_cells_to_pblock -pblock sem -cells [get_cells example_support_wrapper/example_support/sem_controller/*]

The following constraints are also included to force the FRAME_ECC and ICAP placement to the top ICAP but this is not required for monolithic devices (tools can place them correctly with no directives).

# Force FRAME_ECC to the site in this SLR.
set_property LOC CONFIG_SITE_X0Y0 [get_cells example_support_wrapper/example_support/example_cfg/cfg_frame_ecce3]
# Force ICAP to the site in this SLR.
set_property LOC CONFIG_SITE_X0Y0 [get_cells example_support_wrapper/example_support/example_cfg/cfg_icape3]

For SSI implementations, it is important that the FRAME_ECC and ICAP placement constraints are followed to ensure the functionality of the design.