SPI Bus Clock Waveform and Timing Budget - 3.1 English

The SPI flash device has requirements on the switching characteristics of its input clock. This analysis is for the clock signal generated for the SPI flash device by the system-level design example. Completion of this analysis requires board-level signal integrity simulation capability.

The following parameters, shown in the previous figure, are defined as requirements on the clock input to the SPI flash device:

T_clch

SPI bus clock maximum rise time requirement

T_chcl

SPI bus clock maximum fall time requirement

T_cl

SPI bus clock minimum low time requirement

T_ch

SPI bus clock minimum high time requirement

Based on the physical construction of the SPI bus, the I/O characteristics of the FPGA, and the I/O characteristics of any level translator used, the SPI bus clock signal originating at the FPGA exhibits maximum rise and fall times (T_rise and T_fall ) at the SPI flash device. Satisfaction of T_clch and T_chcl requirements by T_rise and T_fall must be verified. Should T_clch and T_chcl requirements not be satisfied, avenues of correction include:

• Change I/O slew rate for the system-level design example SPI bus clock output.
• Change I/O drive strength for the system-level design example SPI bus clock output.
• Select an alternate level translator with more suitable I/O characteristics.

Generally, the T_clch and T_chcl requirements are easy to satisfy. They exist to prohibit exceptionally long rise and fall times that might occur on a true bus with many loads, rather than the point-to-point scheme used with the system-level design example.

The SPI bus clock generated by the system-level design example is the input clock divided by two. Therefore, the SPI bus clock high and low times are nominally equal to T_clk . However, considering actual T_rise and T_fall , also ensure satisfaction of the following:

• T_clk ≥ T_rise + T_ch
• T_clk ≥ T_fall + T_cl

Example :

• T_clch = 33 ns (from SPI flash data sheet)
• T_chcl = 33 ns (from SPI flash data sheet)
• T_cl = 3.375 ns (from SPI flash data sheet)
• T_ch = 3.375 ns (from SPI flash data sheet)
• T_rise = 2 ns (from PCB simulation)
• T_fall = 2 ns (from PCB simulation)

Given this data, perform the following:

1. Check: Is T_clch ≥ T_rise ? Is 33 ns ≥ 2 ns ? Yes
2. Check: Is T_chcl ≥ T_fall ? Is 33 ns ≥ 2 ns ? Yes
3. Calculate: T_clk ≥ T_rise + T_ch requires T_clk ≥ 2 ns + 3.375 ns, or T_clk ≥ 5.375 ns
4. Calculate: T_clk ≥ T_fall + Tcl requires T_clk ≥ 2 ns + 3.375 ns, or T_clk ≥ 5.375 ns

The rise time requirements are satisfied. These requirements on T_clk indicate that the SPI Bus Clock Waveform and Timing Budget restrict the system-level design example input clock cycle time to be 5.375 ns or larger.