System Clock Interface - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

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3.1 English

The following recommendations exist for the system input clock. These recommendations are derived from the FPGA data sheet requirements for clock signals applied to the FPGA configuration system: Duty Cycle: 45% minimum, 55% maximum.

The higher the frequency of the input clock, the lower the mitigation latency of the solution. Therefore, faster is better. There are several important factors that must be considered in determination of the maximum input clock frequency:

  • Frequency must not exceed FPGA configuration system (ICAP) maximum clock frequency. Consult the device data sheet for the target device for this information.
  • Frequency must not exceed the maximum clock frequency as reported in the static timing analyzer. This is generally not a limiting constraint.

Based on the fully synchronous design methodology, additional considerations arise in clock frequency selections that relate to the timing of external interfaces and the system-level design example is used:

  • If the out-of-the-box classification feature using a dedicated SPI flash to store classification data is used:
  • The SPI bus timing budget must be evaluated to determine the maximum SPI bus clock frequency. For more information on a sample analysis, see SPI Bus Timing Budget.
  • The SPI bus clock is the input clock divided by two; therefore, the input clock cannot exceed twice the maximum SPI bus clock frequency.
  • If the UART helper block and UART interface is used for communicating with the controller:
  • The input clock and the serial interface baud rate are related by an integer multiple of 16. For very high baud rates or very low input clock frequencies, the solution space might be limited if standard baud rates are desired.
  • A sample analysis is provided in Switching Behavior.