Unsupported Features - 3.1 English

UltraScale Architecture Soft Error Mitigation Controller LogiCORE IP Product Guide (PG187)

Document ID
PG187
Release Date
2023-11-08
Version
3.1 English

The SEM controller does not operate on soft errors in Block Memory, Distributed Memory, or Flip-Flops. Soft error mitigation in these memory resources must be addressed by the user logic through preventive measures such as redundancy or error detection and correction codes.

Other considerations when you are using the SEM controller in your design include:

  • SEM controller initializes and manages the FPGA integrated silicon features for soft error mitigation and when included in a design, do not include any design constraints or options that would enable the built-in detection functions. For example, do not set POST_CRC, POST_CONFIG_CRC, or any other related constraints. Similarly, do not include options to modify GLUTMASK.
  • Software computed ECC and CRC values are not supported.
  • Design simulations that instantiate the controller are supported. However, it is not possible to observe the controller behaviors in simulation. Design simulation including the controller compiles, but the controller does not exit the initialization state. Hardware-based evaluation of the controller behaviors is required.
  • Use of SelectMAP persistence is not supported by the controller.
  • For UltraScale architecture, each device die or super logic region (SLR) requires a single instance of the SEM controller and ICAP. The ICAP must be placed in the primary/top physical location in that die. If another logic requires access of the configuration memory through the ICAP, the access of the ICAP must be MUXed and shared. Do NOT use BITSTREAM.Readback_ICAP_Select or ICAP_AUTO_SWITCH because these methods are used for switching between the top/bottom ICAP; they not MUX or share the ICAP with other logic.
  • The SEM controller does not operate when a golden or fallback bitstream is loaded by a configuration error and fallback condition from a SPI/BPI flash. See AR 67645.
  • If there are multiple logics accessing the configuration memory, an arbitration logic must be created to manage access to this memory. See ICAP Arbitration Interface.
  • The SEM IP was not developed nor tested for use in space radiation environments. Therefore AMD does not support or answer questions specific to the use of this IP in this environment. If you choose to use the SEM IP in space radiation environments, do so at your own risk.