The SEM controller core has an example design that can be implemented in an FPGA and used to understand the behavior of the IP.
The system-level example design encapsulates the SEM controller and various primitives and helper blocks that serve to interface the Controller to other devices, as shown in Figure 1 .
For designs targeting stacked silicon interconnect (SSI) devices, the system-level example design provides the example of how to mitigate soft errors in each SLR and should be used at the minimum as a guidance. For more information on the delivered example design, see Example Design and for the system-level port solutions, see Port Descriptions.
<component_name>_support_wrapper.vand all of its submodules into the user design, as this contains all integral logic of the total Soft Error Mitigation solution. The solution has been fully verified as delivered. See Structural Options.