AXI Slave Interface - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

For all signals in this interface, s_axi_* is used for the AXI Bridge for PCIe Gen3 core, and s_axib_* is used for the DMA/Bridge Subsystem for PCIe in AXI Bridge mode.

Table 1. AXI Slave Interface Signals
Signal Name I/O Description

s_axi(b)_awid[c_s_axi_id_width-1:0]

 I Slave write address ID

s_axi(b)_awaddr[axi_addr_width-1:0]

 I Slave write address

s_axi(b)_awregion[3:0]

 I Slave write region decode

s_axi(b)_awlen[7:0]

 I Slave write burst length

s_axi(b)_awsize[2:0]

 I Slave write burst size

s_axi(b)_awburst[1:0]

 I Slave write burst type

s_axi(b)_awvalid

 I Slave address write valid

s_axi(b)_awready

 O Slave address write ready

s_axi(b)_wdata[axi_data_width-1:0]

 I Slave write data

s_axi(b)_wstrb[axi_data_width/8-1:0]

 I Slave write strobe

s_axi(b)_wlast

 I Slave write last

s_axi(b)_wvalid

 I Slave write valid

s_axi(b)_wready

 O Slave write ready
s_axi(b)_wuser I Reserved. Tie to GND.
Note: This signal is disabled for AXI Bridge for PCI Express Gen3. This signal is also disabled for the DMA/Bridge Subsystem for PCIe in AXI Bridge mode unless CONFIG.parity_settings = Propagate_Parity is set.

s_axi(b)_bid[c_s_axi_id_width-1:0]

 O Slave response ID

s_axi(b)_bresp[1:0]

 O Slave write response

s_axi(b)_bvalid

 O Slave write response valid

s_axi(b)_bready

 I Slave response ready

s_axi(b)_arid[c_s_axi_id_width-1:0]

 I Slave read address ID

s_axi(b)_araddr[axi_addr_width-1:0]

 I Slave read address

s_axi(b)_arregion[3:0]

 I Slave read region decode

s_axi(b)_arlen[7:0]

 I Slave read burst length

s_axi(b)_arsize[2:0]

 I Slave read burst size

s_axi(b)_arburst[1:0]

 I Slave read burst type

s_axi(b)_arvalid

 I Slave read address valid

s_axi(b)_arready

 O Slave read address ready

s_axi(b)_rid[c_s_axi_id_width-1:0]

 O Slave read ID tag

s_axi(b)_rdata[axi_data_width-1:0]

 O Slave read data

s_axi(b)_rresp[1:0]

 O Slave read response

s_axi(b)_rlast

 O Slave read last

s_axi(b)_rvalid

 O Slave read valid

s_axi(b)_rready

 I Slave read ready
s_axi(b)_ruser O Slave Read ECC Parity.
Note: This signal is disabled for AXI Bridge for PCI Express Gen3. This signal is also disabled for the DMA/Bridge Subsystem for PCIe in AXI Bridge mode unless CONFIG.parity_settings = Propagate_Parity is set.