AXI4-Lite Control Interface - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

For all signals in this interface, s_axi_ctl* is used for the AXI Bridge for PCIe Gen3 core, and s_axil_* is used for the DMA/Bridge Subsystem for PCIe in AXI Bridge mode.

Table 1. AXI4-Lite Control Interface Signals
Signal Name I/O Description

Endpoint configuration: s_axi_ctl_awaddr[11:0] | s_axil_awaddr[31:0]

Root Port configuration: s_axi_ctl_awaddr[27:0] | s_axil_awaddr[31:0]

I Slave write address.

For DMA/Bridge Subsystem for PCIe in AXI Bridge mode, address must always be 512 MB aligned.

s_axil_awaddr[28] = 1'b0 selects Bridge Register Memory Map and Enhanced Configuration Access Memory Map.

s_axil_awaddr[28] = 1'b1 selects DMA/Bridge Subsystem for PCIe Register Memory Map.

For AXI Bridge for PCIe Gen3 core, address must be aligned to 4 KB in Endpoint configuration and 256 MB in Root Port configuration.

s_axi_ctl_awvalid | s_axil_awvalid I Slave write address valid
s_axi_ctl_awready | s_axil_awready O Slave write address ready
s_axi_ctl_wdata[31:0] | s_axil_wdata[31:0] I Slave write data
s_axi_ctl_wstrb[3:0] | s_axil_wstrb[3:0] I Slave write strobe
s_axi_ctl_wvalid | s_axil_wvalid I Slave write valid
s_axi_ctl_wready | s_axil_wready O Slave write ready
s_axi_ctl_bresp[1:0] | s_axil_bresp[1:0] O Slave write response
s_axi_ctl_bvalid | s_axil_bvalid O Slave write response valid
s_axi_ctl_bready | s_axil_bready I Slave response ready

Endpoint configuration: s_axi_ctl_araddr[11:0] | s_axil_araddr[31:0]

Root Port configuration: s_axi_ctl_araddr[27:0] | s_axil_araddr[31:0]

I Slave read address.

For DMA/Bridge Subsystem for PCIe in AXI Bridge mode, the address must always be 512 MB aligned.

s_axil_araddr[28] = 1'b0 selects Bridge Register Memory Map and Enhanced Configuration Access Memory Map

s_axil_araddr[28] = 1'b1 selects DMA/Bridge Subsystem for PCIe Register Memory Map

For AXI Bridge for PCIe Gen3 core, address must be aligned to 4 KB in Endpoint configuration and 256 MB in Root Port configuration.

s_axi_ctl_arvalid | s_axil_arvalid I Slave read address valid
s_axi_ctl_arready | s_axil_arvalid O Slave read address ready
s_axi_ctl_rdata[31:0] | s_axil_arvalid O Slave read data
s_axi_ctl_rresp[1:0] | s_axil_arvalid O Slave read response
s_axi_ctl_rvalid | s_axil_arvalid O Slave read valid
s_axi_ctl_rready | s_axil_arvalid I Slave read ready