Read from a register that does not have all 0s as a default to verify that the
interface is functional. Output
s_axi_arready asserts when the read
address is valid and output
s_axi_rvalid asserts when
the read data/response is valid. If the interface is unresponsive ensure that the
following conditions are met.
- For older versions of the AXI Bridge for PCIe
Gen3 core with the
axi_ctl_aclkport, ensure the
axi_ctl_aclk_outpins are connected to the design and are pulsing out of the IP.
- The interface is not being held in reset, and
axi_aresetnis an active-Low reset.
- Ensure that the main core clocks are toggling and that the enables are also asserted.
- Has a simulation been run? Verify in simulation and/or a AMD Vivado™ Design Suite debug feature capture that the waveform is correct for accessing the AXI4-Lite interface.