Addressing Checks - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

When setting the following parameters for PCIe® address mapping, C_PCIEBAR2AXIBAR_n and PF0_BARn_APERTURE_SIZE, be sure these are set to allow for the addressing space on the AXI system. For example, the following setting is illegal and results in an invalid AXI address.

C_PCIEBAR2AXIBAR_n=0x00000000_FFFFF000
PF0_BARn_APERTURE_SIZE=0x06 (8 KB)

For an 8 Kilobyte BAR, the lower 13 bits must be zero. As a result, the C_PCIEBAR2AXIBAR_n value should be modified to be 0x00000000_FFFFE0000. Also, check for a larger value on PF0_BARn_APERTURE_SIZE compared to the value assigned to the C_PCIEBAR2AXIBAR_n parameter. And example parameter setting follows.

C_PCIEBAR2AXIBAR_n=0xFFFF_E000
PF0_BARn_APERTURE_SIZE=0x0D (1 MB)

To keep the AXIBAR upper address bits as 0xFFFF_E000 (to reference bits [31:13]), the PF0_BARn_APERTURE_SIZE parameter must be set to 0x06 (8 KB).