Architecture - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The Endpoint model consists of these blocks:

  • PCI Express Endpoint (Bridge in Endpoint configuration) model.
  • PIO slave design, consisting of:
  • pio_rx_engine
  • pio_tx_engine
  • pio_ep_mem
  • pio_to_ctrl

The pio_rx_engine and pio_tx_engine blocks interface with the ep block for reception and transmission of TLPs from/to the Root Port Design Under Test (DUT). The Root Port DUT consists of the core configured as a Root Port and the Block RAM controller along with s_axi and s_axi_ctl models to drive traffic on s_axi and s_axi_ctl.