Bridge Info Register (Offset 0x130) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The Bridge Info register (described in the following table) provides general configuration information about the AXI4-Stream Bridge. Information in this register is static and does not change during operation.

Table 1. Bridge Info Register
Bits Name Core Access Reset Value Description
0 Gen2 Capable RO 0 If set, underlying integrated block supports PCIe® Gen2 speed.
1 Root Port Present RO 0

Indicates the underlying integrated block is a Root Port when this bit is set.

If set, Root Port registers are present in this interface.

2 Reserved RO 0 Reserved
3 Gen3 Capable RO 0 If set, underlying integrated block supports PCIe Gen3 speed.
31:4 Reserved RO 0 Reserved