Bridge Register Memory Map - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English
Table 1. Bridge Register Memory Map
Accessibility Offset Contents Location
RO - EP 0x000 -0xFF PCIe® Configuration Space Header

For more details of the register layout for addresses in this address range:

For Virtex-7 XT, see Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)

For UltraScale, see UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

For UltraScale+, see UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)

Part of the integrated PCIe® configuration space.
RO - EP 0x100-0x124

PCIe® Extended Configuration Space Header

For more details of the register layout for addresses in this address range:

For Virtex-7 XT, see Virtex-7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)

For UltraScale, see UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)

For UltraScale+, see UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)

Part of the integrated PCIe® configuration space.
RO 0x128 PCIe® Vendor Specific Extended Capability Header for Bridge register AXI bridge defined memory-mapped register space.
RO 0x12C PCIe® Vendor Specific Header for Bridge register
RO 0x130 Bridge Info
RO - EP 0x134 Bridge Status and Control
R/W 0x138 Interrupt Decode
R/W 0x13C Interrupt Mask
RO - EP 0x140 Bus Location
RO 0x144 Physical-Side Interface (PHY) Status/Control
RO - EP, R/W - RC 0x148 Root Port Status/Control
RO - EP, R/W - RC 0x14C Root Port MSI Base 1
RO - EP, R/W - RC 0x150 Root Port MSI Base 2
RO - EP, R/W - RC 0x154 Root Port Error FIFO Read
RO - EP, R/W - RC 0x158 Root Port Interrupt FIFO Read 1
RO - EP, R/W - RC 0x15C Root Port Interrupt FIFO Read 2
RO 0x160

Reserved for AXI PCIe® Bridge.

Interrupt Decode 2 for the DMA/Bridge Subsystem for PCI Express, when configured in Bridge mode ( UltraScale+™ ).

AXI bridge defined memory-mapped register space.
RO 0x164

Reserved for AXI PCIe® Bridge.

Interrupt Decode 2 for the DMA/Bridge Subsystem for PCI Express, when configured in Bridge mode ( UltraScale+™ ).

R/W 0x168 Configuration Control
R/W 0x170

Reserved for AXI PCIe 3 Bridge.

Root Port MSI Interrupt Decode 1 Register for the DMA/Bridge Subsystem for PCI Express core when configured in Bridge mode (UltraScale+).

R/W 0x174

Reserved for AXI PCIe® 3 Bridge.

Root Port MSI Interrupt Decode 2 Register for the DMA/Bridge Subsystem for PCI Express, when configured in Bridge mode (UltraScale+).

R/W 0x178

Reserved for AXI PCIe® 3 Bridge.

Root Port MSI Interrupt Decode 1 Mask Register for the DMA/Bridge Subsystem for PCI Express, when configured in Bridge mode core (UltraScale+).

R/W 0x17C

Reserved for AXI PCIe® 3 Bridge.

Root Port MSI Interrupt Decode 2 Mask Register for the DMA/Bridge Subsystem for PCI Express, when configured in Bridge mode (UltraScale+).

RO 0x180 - 0x1FF Reserved (zeros returned on read)
RO 0x200 VSEC Capability 2
RO 0x204 VSEC Header 2
R/W 0x208 - 0x234 AXI Base Address Translation Configuration Registers
RO 0x238 - 0xFFF Reserved (zeros returned on read)

The Bridge register is mapped within the PCIe® Extended Configuration Space Header memory region. The AXI Bridge VSEC registers are only accessible from the Bridge IP AXI4-Lite Control Interface, therefore at the start of the PCIe® Extended Configuration Space (offset 0x100), the capability header will point to address 0x128 as the next capability pointer. When the PCIe® Extended Configuration Space is accessed from the PCIe link, the next capability pointer field will point to the next enabled PCIe® capability instead of the AXI Bridge VSEC register.