Bridge Status and Control Register (Offset 0x134) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

The Bridge Status and Control register (described in the following table) provides information about the current state of the AXI4-Stream Bridge. It also provides control over how reads and writes to the Core Configuration Access aperture are handled.

Table 1. Bridge Status and Control Register
Bits Name Core Access Reset Value Description
7:0 Reserved RO 0 Reserved
8

Global

Disable

RW 0 When set, disables interrupt line from being asserted. Does not prevent bits in Interrupt Decode register from being set.
31:9 Reserved RO 0 Reserved