The Bus Location register reports the Bus, Device, and Function number, and the Port number for the PCIe port (see the following table).
|Bits||Name||Core Access||Reset Value||Description|
|2:0||Function Number||RO||0||Function number of the port for PCIe. Hard-wired to 0.|
|7:3||Device Number||RO||0||Device number of port for PCIe. For Endpoint, this register is RO and is set by the Root Port.|
|15:8||Bus Number||RO||0||Bus number of port for PCIe. For Endpoint, this register is RO and is set by the external Root Port.|
Sets the Port number field of the Link Capabilities register.
EP: Always Read 0 and is not writeable.
RP: Is writeable.