Clocking - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The reference clock input is used to generate the internal clocks used by the core and the output clock. Note that the reference clock is refclk in Virtex®-7 devices, and sys_clk_gt in UltraScale™ ™ and UltraScale+™ ™ devices. This clock must be provided at the reference clock frequency selected in the Vivado® Integrated Design Environment (IDE) during IP generation. This port should be driven by the PCI Express edge connector clock pins through an IBUFDSGTE primitive.

The axi_aclk output is the clock used for all AXI interfaces and should drive all corresponding AXI Interconnect aclk signals as well as the axi_ctl_aclk input port when using the older version of the AXI Bridge for PCI Express Gen3 core with the axi_ctl_aclk port available externally.

Note: The axi_aclk output should not be used for the system clock for your design. The axi_aclk is not a free-run clock output. As noted, axi_aclk may not be present at all times.

For additional information about how the source of the aclk clock might impact your designs, see the 7 Series FPGAs Clocking Resources User Guide (UG472), or the UltraScale Architecture Clocking Resources User Guide (UG572).

The following figure shows the clocking diagram for the core in an UltraScale device.

Figure 1. Clocking Diagram (UltraScale Devices)

The following figure shows the clocking diagram for the core in an UltraScale™ device.

Figure 2. Clocking Diagram (UltraScale+ Devices)

Table 1. Clock Frequencies and Interface Widths Supported For Various Configurations
PCIe Link Speed Capability PCIe Link Width Capability AXI4 Memory Mapped Interface Data Width (bits) user_clk2 Frequency (MHz) (AXI4-Stream)
Gen1 X1 64 62.5
64 125
64 250
X2 64 62.5
64 125
64 250
X4 64 125
64 250
X8 64 250
128 125
X16 128 250
Gen2 X1 64 62.5
64 125
64 250
X2 64 125
64 250
X4 64 250
128 125
X8 128 250
256 125
X16 256 250
Gen3 X1 64 125
64 250
X2 64 250
128 125
X4 128 250
256 125
X8 256 250
256 250
X16 512 250
Gen4 2 X1 64 250
128 125
X2 128 250
256 125
X4 256 250
X8 512 250
  1. All X16 rows (Gen1/2/3) exist in DMA/Bridge Subsystem for PCIe in AXI Bridge mode only.
  2. All Gen4 rows are only applicable to Virtex® UltraScale+™ devices with high bandwidth memory (HBM) (PCIE4C).