Clocking - 3.0 English

The reference clock input is used to generate the internal clocks used by the core and the output clock. Note that the reference clock is refclk in Virtex®-7 devices, and sys_clk_gt in UltraScale™ ™ and UltraScale+™ ™ devices. This clock must be provided at the reference clock frequency selected in the Vivado® Integrated Design Environment (IDE) during IP generation. This port should be driven by the PCI Express edge connector clock pins through an IBUFDSGTE primitive.

The axi_aclk output is the clock used for all AXI interfaces and should drive all corresponding AXI Interconnect aclk signals as well as the axi_ctl_aclk input port when using the older version of the AXI Bridge for PCI Express Gen3 core with the axi_ctl_aclk port available externally.

For additional information about how the source of the aclk clock might impact your designs, see the 7 Series FPGAs Clocking Resources User Guide (UG472), or the UltraScale Architecture Clocking Resources User Guide (UG572).

The following figure shows the clocking diagram for the core in an UltraScale device.

Figure 1. Clocking Diagram (UltraScale Devices)

The following figure shows the clocking diagram for the core in an UltraScale™ device.

Figure 2. Clocking Diagram (UltraScale+ Devices)