Configuration Control Register (Offset 0x168) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

Configuration Control register (described in the following table) allows the user application to indicate if a correctable or uncorrectable error has occurred and report it in the respective AER Error Status Register.

Table 1. Configuration Control Register
Bits Name Core Access Reset Value Description
0 Uncorrectable Error RW 0

Uncorrectable Error Detected. The user application writes a 1 to this bit to indicate an Uncorrectable error was detected within the user logic that needs to be reported as an internal error through the PCI Express Advanced Error Reporting mechanism. In response, the core sets the Uncorrected Internal Error Status bit in the AER Uncorrectable Error Status Register of all enabled functions, and also sends an error message if enabled to do so. This error is not considered function-specific.

This bit only asserts for 1 clock cycle and automatically resets to 0 in the next clock cycle.

1 Correctable Error RW 0

Correctable Error Detected. The user application writes a 1 to this bit to indicate a Correctable error was detected within the user logic that needs to be reported as an internal error through the PCI Express Advanced Error Reporting mechanism. In response, the core sets the Corrected Internal Error Status bit in the AER Correctable Error Status Register of all enabled functions, and also sends an error message if enabled to do so. This error is not considered function-specific.

This bit only asserts for 1 clock cycle and automatically resets to 0 in the next clock cycle.

31:2 Reserved RO 0 Reserved