Connecting the Vivado Design Suite to the XVC-Server Application - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English
The Vivado Design Suite can be run on the computer that is running the XVC-server application, or it can be run remotely on another computer that is connected over an Ethernet network. The port however must be accessible to the machine running Vivado. To connect Vivado to the XVC-Server application follow the steps should be used and are shown using the default port number.
  1. Launch the Vivado Design Suite.
  2. Select Open HW Manager.
  3. In the Hardware Manager, select Open target > Open New Target.
  4. Click Next.
  5. Select Local server, and click Next.

    This launches hw_server on the local machine, which then connects to the xvcserver application.

  6. Select Add Xilinx Virtual Cable (XVC).
  7. In the Add Virtual Cable dialog box, type in the appropriate Host name or IP address, and Port to connect to the xvcserver application. Click OK.

  8. Select the newly added XVC target from the Hardware Targets table, and click Next.

  9. Click Finish.
  10. In the Hardware Device Properties panel, select the debug bridge target, and assign the appropriate probes .ltx file.

Vivado now recognizes your debug cores and debug signals, and you can debug your design through the Vivado hardware tools interface using the standard debug approach.

This allows you to debug Xilinx FPGA designs through the PCIe connection rather than JTAG using the Xilinx Virtual Cable technology. You can terminate the connection by closing the hardware server from Vivado using the right-click menu. If the PCIe connection is lost or the XVC-Server application stops running, the connection to the FPGA and associated debug cores will also be lost.