- Launch the Vivado Design Suite.
- Select Open HW Manager.
- In the Hardware Manager, select .
- Click Next.
- Select Local server, and
This launches hw_server on the local machine, which then connects to the xvcserver application.
- Select Add Xilinx Virtual Cable (XVC).
- In the Add Virtual Cable dialog box, type in the appropriate Host name or IP
address, and Port to connect to the xvcserver application. Click OK.
- Select the newly added XVC target from the Hardware Targets
table, and click Next.
- Click Finish.
- In the Hardware Device Properties panel, select the debug bridge target, and
assign the appropriate probes .ltx
Vivado now recognizes your debug cores and debug signals, and you can debug your design through the Vivado hardware tools interface using the standard debug approach.
This allows you to debug Xilinx FPGA designs through the PCIe connection rather than JTAG using the Xilinx Virtual Cable technology. You can terminate the connection by closing the hardware server from Vivado using the right-click menu. If the PCIe connection is lost or the XVC-Server application stops running, the connection to the FPGA and associated debug cores will also be lost.