This section lists Interrupt registers that are unique to DMA/Bridge Subsystem for
PCIe in AXI Bridge mode only. These registers listed in
this section are accessible through the AXI4-Lite Control interface when
address bit is set to
1'b1. When address bit is set to
1'b0, all of these register fields are re-purposed for Bridge operation,
which contains the same Bridge Memory map layout as listed in the previous section.
|Reserved||Register Table Select||Reserved||Target||Reserved||Byte Offset|
|28||Register Table Select||
1'b0: Select Bridge and ECAM registers listed in Bridge Memory Map in the previous section.
1'b1: Select Interrupt registers listed in this section.
When bit = 1'b0: Refer to Bridge Memory map.
When bit = 1'b1: Reserved
The destination submodule within the DMA
4’h2: IRQ Block
|11:8||Reserved||This field must be 0.|
|7:0||Byte Offset||The byte address of the register to be accessed within the target. Bits[1:0] must be 0.|