DMA/Bridge Subsystem for PCIe in Bridge Mode Interrupt Signals - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

The interface signals for the Bridge are described in the following table.

Table 1. DMA/Bridge Subsystem for PCIe in Bridge Mode Interrupt Signals
Signal Name I/O Description
usr_irq_req[NUM_USR_IRQ-1:0] I Assert to generate an interrupt. Maintain assertion until interrupt is serviced.
usr_irq_ack[NUM_USR_IRQ-1:0] O Indicates that the interrupt has been sent on PCIe. Two acks are generated for legacy interrupts. One ack is generated for MSI interrupts.
msi_enable O Indicates when MSI is enabled.
msix_enable O Indicates when MSI-X is enabled.