This example shows the generic settings to set up two independent BARs for PCIe® and address translation of addresses for PCIe to a remote AXI address space. This setting of BARs for PCIe does not depend on the AXI BARs within the bridge.
In this example, where C_PCIEBAR_NUM=2, the following range assignments are made.
AXI_ADDR_WIDTH=48
BAR 0 is set to 0x20000000_ABCD8000 by the Root Port. (Since this is a 64-bit BAR
PCIe, BAR1 is disabled.)
PF0_BAR0_APERTURE_SIZE=0x08 (32 Kbytes)
C_PCIEBAR2AXIBAR_0=0x00000000_12340000 (Because the AXI address is 48-bits wide,
bits 63-48 should be zero. Base on the PCIe Bar Size bits 14-0 should be zero.
Non-zero values in these ranges are invalid.)
BAR 2 is set to 0xA000000012000000 by Root Port. (Since this is a 64-bit BAR PCIe BAR3
is disabled.)
PF0_BAR0_APERTURE_SIZE=0x12 (32 Mbytes)
C_PCIEBAR2AXIBAR_2=0x00000000_FE000000 (Because the AXI address is 48-bits wide,
bits 63-48 should be zero. Base on the PCIe Bar Size bits 24-0 should be zero.
Non-zero values in these ranges are invalid.)
Figure 1. Example 3 Settings
- Accessing the Bridge PCIEBAR_0 with address 0x20000000_ABCDFFF4 on the PCIe bus yields 0x0000_12347FF4 on the AXI Bus.
Figure 2.
PCIe to AXI
Translation
- Accessing Bridge PCIEBAR_2 with address 0xA00000000_1235FEDC on the PCIe bus yields 0x0000_FE35FEDC on the AXI bus.