Example 4 - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

This example shows the generic settings of four AXI BARs and address translation of AXI addresses to a remote 32-bit and 64-bit addresses for PCIe® . This setting of AXI BARs do not depend on the BARs for PCIe within the Bridge.

In this example, where number AXI BAR's are 4, the following assignments for each range are made:



Aperture_Base_Address_0 =0x00000000_12340000
Aperture_High_Address_0 =0x00000000_1234FFFF (64 KB)
AXI_to_PCIe_Translation_0=0x00000000_56710000 (Bits 63-32 are zero to produce a 32-bit PCIe 
TLP. Bits 15-0 must be zero based on the AXI BAR aperture size. Non-zero values in 
the lower 16 bits are invalid translation values.)

Aperture_Base_Address_1 =0x00000000_ABCDE000
Aperture_High_Address_1 =0x00000000_ABCDFFFF (8 KB)
AXI_to_PCIe_Translation_1=0x50000000_FEDC0000 (Bits 63-32 are non-zero to produce a 64-bit 
PCIe TLP. Bits 12-0 must be zero based on the AXI BAR aperture size. Non-zero values 
in the lower 13 bits are invalid translation values.)

Aperture_Base_Address_2 =0x00000000_FE000000
Aperture_High_Address_2 =0x00000000_FFFFFFFF (32 MB)
AXI_to_PCIe_Translation_2=0x00000000_40000000 (Bits 63-32 are zero to produce a 32-bit PCIe 
TLP. Bits 24-0 must be zero based on the AXI BAR aperture size. Non-zero values in 
the lower 25 bits are invalid translation values.)

Aperture_Base_Address_3 =0x00000000_00000000
Aperture_High_Address_3 =0x00000000_00000FFF (4 KB)
AXI_to_PCIe_Translation_3=0x60000000_87654000 (Bits 63-32 are non-zero to produce a 64-bit 
PCIe TLP. Bits 11-0 must be zero based on the AXI BAR aperture size. Non-zero values 
in the lower 12 bits are invalid translation values.)


Figure 1. Example 4 Settings

  • Accessing the Bridge AXI BAR_0 with address 0x0000_12340ABC on the AXI bus yields 0x56710ABC on the bus for PCIe.
  • Accessing the Bridge AXI BAR_1 with address 0x0000_ABCDF123 on the AXI bus yields 0x50000000FEDC1123 on the bus for PCIe.
  • Accessing the Bridge AX IBAR_2 with address 0x0000_FFFEDCBA on the AXI bus yields 0x41FEDCBA on the bus for PCIe.
  • Accessing the Bridge AXI BAR_3 with address 0x0000_00000071 on the AXI bus yields 0x6000000087654071 on the bus for PCIe.