In Root Port configuration, the slave AXI4-Lite and slave
AXI4 interfaces are typically driven by a PS system or a
. This microprocessor runs a kernel driver software
that will do PCIe enumeration process. The Master AXI
interface is connected if there is a packet generator module at the Endpoint side, such
as a DMA engine. The
interrupt_out signal is typically connected to the
Processor Interrupt Controller and multiplexed together with other interrupt sources
before being forwarded to the kernel driver software running at the microprocessor.
In Endpoint configuration, the Slave AXI interface is typically driven by a DMA module or a packet generator, such as an AXI exerciser. The master AXI4 interface is used to receive packets from the host, such as the DMA configuration file or PIO, and accesses directly to a Memory module, such as MIG. The slave AXI4-Lite interface is not typically used in an Endpoint configuration but can be utilized to check some Bridge/Link status registers. The User Interrupt input signals can be driven by an Interrupt controller to signal the Host for any important event at the Endpoint side, such as a DMA transfer complete and an error event.
The following figure shows an example of where the Bridge cores can be used.