The core supports the MSI-X interrupt and its signaling. The MSI-X vector table and the MSI-X Pending Bit Array need to be implemented as part of the user logic, by claiming a BAR aperture. The External MSI-X interrupts mode is enabled when you set the MSI-X Implementation Location option to External in the PCIe Misc Tab.
To send MSI-X interrupt, user logic must use
cfg_interrupt_msix_* interface instead of the intx_msi_* interface. The
signaling requirement is the same as defined in the UltraScale Devices Gen3 Integrated
Block for PCIe core as shown below.