Feature Summary - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The Bridge core is an interface between the AXI4 bus and PCI Express® . The core contains the memory mapped AXI4 to AXI4-Stream Bridge and the AXI4-Stream Enhanced Interface Block for PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a register block and two functional half bridges, referred to as the Slave Bridge and Master Bridge. The slave bridge connects to the AXI4 Interconnect as a slave device to handle any issued AXI4 master read or write requests. The master bridge connects to the AXI4 interconnect as a master to process the PCIe generated read or write TLPs. The core uses a set of interrupts to detect and flag error conditions.

The Bridge core supports both Root Port and Endpoint configurations.

  • When configured as an Endpoint, the Bridge core supports up to six 32-bit or three 64-bit PCIe Base Address Registers (BARs).
  • When configured as a Root Port, the core supports up to two 32-bit or a single 64-bit PCIe BAR.

The Bridge core is compliant with the PCI-SIG Specifications (https://www.pcisig.com/specifications) and with the AMBA AXI and ACE Protocol Specification (ARM IHI0022E).