Features - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English
  • AXI Bridge for PCI Express Gen3 supports UltraScale™ architecture and Virtex®-7 XT FPGA Gen3 Integrated Blocks for PCI Express®
  • DMA/Bridge Subsystem for PCI Express core in AXI Bridge mode supports UltraScale+ Integrated Blocks for PCI Express
  • AXI Bridge for PCI Express Gen3 supports Maximum Payload Size (MPS) up to 512 bytes
  • DMA/Bridge Subsystem for PCI Express core in AXI Bridge mode supports Maximum Payload Size (MPS) up to 1024 bytes
  • Multiple Vector Messaged Signaled Interrupts (MSIs)
  • MSI-X interrupt support
  • Legacy interrupt support
  • Memory-mapped AXI4 access to PCIe® space
  • PCIe access to memory-mapped AXI4 space
  • Tracks and manages Transaction Layer Packets (TLPs) completion processing
  • Detects and indicates error conditions with interrupts
  • Optimal AXI4 pipeline support for enhanced performance
  • Compliant with Advanced RISC Machine Arm® Advanced Microcontroller Bus Architecture 4 ( AMBA® ) AXI4 specification
  • Supports up to six PCIe 32-bit or three 64-bit PCIe Base Address Registers (BARs) as Endpoint
  • Supports up to two PCIe 32-bit or a single PCIe 64-bit BAR as Root Port