Generating a PCIe-XVC-VSEC Example Design - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The PCIe-XVC-VSEC can be added to the UltraScale+™ PCIe example design by selecting the following options.

  1. Configure the core to the desired configuration.
  2. On the Basic tab, select the Advanced Mode.
  3. On the Adv. Options-3 tab:
    1. Select the PCI Express Extended Configuration Space Enable checkbox to enable the PCI Express extended configuration interface. This is where additional extended capabilities can be added to the PCI Express core.
    2. Select the Add the PCIe-XVC-VSEC to the Example Design checkbox to enable the PCIe-XVC-VSEC in the example design generation.
  4. Verify the other configuration selections for the PCIe IP. The following selections are needed to configure the driver for your hardware implementation:
    • PCIe Vendor ID (0x10EE for Xilinx)
    • PCIe Device ID (dependent on user selection)
  5. Click OK to finalize the selection and generate the IP.
  6. Generate the output products for the IP as desired for your application.
  7. In the Sources window, right-click the IP and select Open IP Example Design.
  8. Select a directory for generating the example design, and select OK.
    After being generated, the example design shows that:
    • the PCIe IP is connected to xvc_vsec within the support wrapper, and
    • an ILA IP is added to the user application portion of the design.

    This demonstrates the desired connectivity for the hardware portion of the FPGA design. Additional debug cores can be added as required by your application.

    Note: Although the previous figure shows to the UltraScale+ Devices Integrated Block for PCIe IP, the example design hierarchy is the same for other PCIe IPs.
  9. Double-click the Debug Bridge IP identified as xvc_vsec to view the configuration option for this IP. Make note of the following configuration parameters because they will be used to configure the driver.
    • PCIe XVC VSEC ID (default 0x0008)
    • PCIe XVC VSEC Rev ID (default 0x0)
    Important: Do not modify these parameter values when using a Xilinx Vendor ID or provided XVC drivers and software. These values are used to detect the XVC extended capability. (See the PCIe specification for additional details.)
  10. In the Flow Navigator, click Generate Bitstream to generate a bitstream for the example design project. This bitstream will be then be loaded onto the FPGA board to enable XVC debug over PCIe.

After the XVC-over-PCIe hardware design has been completed, an appropriate XVC enabled PCIe driver and associated XVC-Server software application can be used to connect the Vivado Design Suite to the PCIe connected FPGA. Vivado can connect to an XVC-Server application that is running local on the same Machine or remotely on another machine using a TCP/IP socket.