Global Signals - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The interface signals for the Bridge are described in the following table.

Table 1. Global Signals
Signal Name I/O Description
refclk I AXI Bridge for PCIe Gen3 only:

Virtex®-7: PCIe Reference Clock. Should be driven from the O port of reference clock IBUFDS_GTE2.

UltraScale™ : Dynamic reconfiguration port (DRP) Clock and Internal System Clock (Half frequency from sys_clk_gt frequency if PCIe Reference Clock is 250 MHz, otherwise same frequency as sys_clk_gt frequency). Should be driven by the ODIV2 port of reference clock IBUFDS_GTE3.

sys_clk I DMA/Bridge Subsystem for PCIe in AXI Bridge mode only:

UltraScale+: Dynamic reconfiguration port (DRP) Clock and Internal System Clock (Half frequency from sys_clk_gt frequency if PCIe Reference Clock is 250 MHz, otherwise same frequency as sys_clk_gt frequency). Should be driven by the ODIV2 port of reference clock IBUFDS_GTE4.

sys_clk_gt I PCIe Reference Clock.

UltraScale: Should be driven from the O port of reference clock IBUFDS_GTE3.

UltraScale+: Should be driven from the O port of reference clock IBUFDS_GTE4.

sys_rst_n I Reset from the PCIe edge connector reset signal.
axi_aclk O AXI Bridge for PCIe Gen3: PCIe derived clock output for M_AXI, S_AXI interfaces, and all interrupt sideband (MSI, MSI-X, and Bridge Mode Interrupt) signals.

DMA/Bridge Subsystem for PCIe in AXI Bridge mode: PCIe derived clock output for M_AXIB, S_AXIB, and S_AXIL interfaces. axi_aclk is a derived clock from the TXOUTCLK pin from the GT block; it is not expected to run continuously while axi_aresetn is asserted.

axi_ctl_aclk I AXI Bridge for PCIe Gen3 only:

aclk for the S_AXI_CTL interface. Recommended to be driven by the axi_aclk output. axi_ctl_aclk is a derived clock from the TXOUTCLK pin from the GT block; it is not expected to run continuously while axi_ctl_aresetn is asserted.

This pin is for legacy use mode only. By default, new IP generation will have this clock pin internally driven by the IP. Use axi_aclk pin to clock the design.

interrupt_out O Interrupt signal. It is asserted for as long as there exists at least one bit asserted in the Interrupt Decode register and is not masked in the Interrupt Mask register, and/or asserted in the Interrupt Decode 2 register and is not masked in the Interrupt Decode 2 Mask register.
interrupt_out_msi_vec0to31 O Interrupt signal. It is asserted for as long as there exists at least one bit asserted in the Root Port MSI Interrupt Decode 1 register and is not masked in the Root Port MSI Interrupt Decode 1 Mask register.

Only available in Root Port configuration with Interrupt Decode mode

interrupt_out_msi_vec32to63 O Interrupt signal. It is asserted for as long as there exists at least one bit asserted in the Root Port MSI Interrupt Decode 2 register and is not masked in the Root Port MSI Interrupt Decode 2 Mask register.

Only available in Root Port configuration with Interrupt Decode mode.

axi_aresetn O AXI Bridge for PCIe Gen3: Reset signal for the S_AXI and M_AXI interfaces. axi_aresetn deasserts after a function has transitioned into D0_active power state (configured and enabled).

DMA/Bridge Subsystem for PCIe in AXI Bridge mode:

In Endpoint configuration, reset signal for the S_AXIB and M_AXIB interfaces. axi_aresetn deasserts after a function has transitioned into D0_active power state (configured and enabled).

In Root Port configuration, axi_aresetn deasserts after GT transceivers are initialized (assertion of Phy Ready, independent from PCIe link status).

Important: The default value of this pin in the DMA/Bridge Subsystem for PCIe in AXI Bridge mode has changed as mentioned above.
axi_ctl_aresetn O AXI Bridge for PCIe Gen3: Reset signal for the S_AXI_CTL interface. axi_ctl_aresetn deasserts after two axi_ctl_aclk (or axi_aclk for newer IP that does not have the axi_ctl_aresetn pin) cycles after sys_rst_n deasserts.

DMA/Bridge Subsystem for PCIe in AXI Bridge mode: Reset signal for the S_AXIL interface. In Endpoint configuration, axi_ctl_aresetn deasserts after a function has transitioned into D0_active power state (configured and enabled). In Root Port configuration, axi_ctl_aresetn deasserts after GT transceivers are initialized (assertion of Phy Ready, independent from PCIe link status).

Important: The default value of this pin in the DMA/Bridge Subsystem for PCIe in AXI Bridge mode has changed as mentioned above.
dma_bridge_resetn I Optional pin available to DMA/Bridge Subsystem for PCIe in AXI Bridge mode only and appears only when SOFT_RESET_EN parameter is set to TRUE. This pin is intended to be user driven reset when link down, Function Level Reset, Dynamic Function eXchange, or another error condition defined by user has occurred. It is not required to be toggled during initial link up operation.

When used, all PCIe traffic must be in quiesce state. The signal must be asserted for longer than the Completion Timeout value (typically 50 ms).

0: Resets all internal Bridge engines and registers as well as asserts axi_aresetn and axi_ctl_aresetn signals while maintaining PCIe link up.

1: Normal operation.