The sys_reset_n input should be driven directly by FPGA I/O pins. The pin should
be driven by the
PCI Express®
edge connector reset signal
(perstn). As described in the
PCI Express®
Specification, the PCI Express edge connector reset is driven at
3.3V. If the bank voltage for the sys_reset_n pin differs from 3.3V,
and external level shifter is required to convert the 3.3V PCI Express edge connector reset (perstn) to the desired FPGA bank voltage.