IP Facts - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family AXI Bridge for PCIe Gen3: UltraScale, Virtex-7 XT 1

DMA/Bridge Subsystem for PCIe in AXI Bridge mode: UltraScale+

Supported User Interfaces AXI4
Resources Performance and Resource Utilization web page
Provided with Core
Design Files Verilog
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Not Provided
Supported S/W Driver Root Port Driver
Tested Design Flows 2
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide
Synthesis Vivado synthesis
Support
Release Notes and Known Issues Master Answer Record: 61898
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. Except for XC7VX485T, XC7V585T, and XC7V2000T, all Virtex-7 devices are supported.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.