Legacy Interrupts - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

Asserting one or more bits of usr_irq_req when legacy interrupts are enabled causes the IP to issue a legacy interrupt over PCIe. Multiple bits may be asserted simultaneously but each bit must remain asserted until the corresponding usr_irq_ack bit has been asserted. After a usr_irq_req bit is asserted, it must remain asserted until the corresponding usr_irq_ack bit is asserted and the interrupt has been serviced and cleared by the Host. The usr_irq_ack assertion indicates the requested interrupt has been sent on the PCIe block. This will ensure interrupt pending register within the IP remains asserted when queried by the Host's Interrupt Service Routine (ISR) to determine the source of interrupts. You must implement a mechanism in the user application to know when the interrupt routine has been serviced. This detection can be done in many different ways depending on your application and your use of this interrupt pin. This typically involves a register (or array of registers) implemented in the user application that is cleared, read, or modified by the Host software when an interrupt is serviced.

After the usr_irq_req bit is deasserted, it cannot be reasserted until the corresponding usr_irq_ack bit has been asserted for a second time. This indicates the deassertion message for the legacy interrupt has been sent over PCIe. After a second usr_irq_ack occurred, the usr_irq_req wire can be reasserted to generate another legacy interrupt.

The usr_irq_req bit can be mapped to legacy interrupt INTA, INTB, INTC, INTD through the configuration registers. The following figure shows the legacy interrupts.

This figure shows only the handshake between usr_irq_req and usr_irq_ack . The user application might not clear or service the interrupt immediately, in which case, you must keep usr_irq_req asserted past usr_irq_ack .

Figure 1. Legacy Interrupts