Limitations - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English
  1. For this subsystem, the bridge master and bridge slave cannot achieve more than 128 Gb/s.

  2. Bridge will be compliant with all MPS and MRRS settings; however, all traffic initiated from the Bridge will be limited to 256 Bytes (max).
  3. AXI address width is limited to 48 bits.