MSI Interrupt - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The IP decodes the MSI interrupt based on the value programmed in Root Port MSI Base Register 1 and Root Port MSI Base Register 2. Any Memory Write TLPs received from the link with an address that falls within the 4 Kb window from the base address programmed in those registers will be treated as MSI interrupt, and will not be forwarded to the M_AXI(B) interface.

Note: MSI Message Data [5:0] will always be decoded as MSI Message vector regardless of how many vectors are enabled at your Endpoint.

When an MSI interrupt is received, the Root Port MSI Interrupt Decode 1 or Root Port MSI Interrupt Decode 2 register is set. If the Root Port MSI Interrupt Decode 1 or Root Port MSI Interrupt Decode 2 register is also set, the interrupt_out_msi_vec* pins are asserted. interrupt_out_msi_vec0to31 corresponds to MSI vector 0 - 31, and interrupt_out_msi_vec32to63 corresponds to MSI vector 32 - 63. After receiving this interrupt, the user application must follow this procedure to service the interrupt:

  1. Optional: Write 0 to the Root Port MSI Interrupt Decode 1 or 2 Mask register to deassert the interrupt_out_msi_vec* pins while the interrupt is being serviced.
  2. Read the Root Port MSI Interrupt Decode 1 or 2 register to check which interrupt vector is asserted.
  3. Write 1 to the Root Port MSI Interrupt Decode 1 or 2 register to clear the MSI interrupt bit.
  4. If step 1 was executed, write 1 to the Root Port MSI Interrupt Decode 1 or 2 Mask register bit to re-enable the interrupt_out_msi_vec* pins for future MSI interrupts.