MSI-X Vector Table and PBA (0x8) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

The MSI-X Vector table and PBA are described in the following table.

Table 1. MSI-X Vector Table and PBA (0x00–0xFE0)
Byte Offset Bit Index Default Access Type Description
0x00 31:0 32’h0 RW MSIX_Vector0_Address[31:0] MSI-X vector0 message lower address.
0x04 31:0 32’h0 RW MSIX_Vector0_Address[63:32] MSI-X vector0 message upper address.
0x08 31:0 32’h0 RW MSIX_Vector0_Data[31:0] MSI-X vector0 message data.
0x0C 31:0 32’h0 RW

MSIX_Vector0_Control[31:0]

MSI-X vector0 control.

Bit Position:

31:1: Reserved.

0: Mask. When set to one, this MSI-X vector is not used to generate a message.

0x1F0 31:0 32’h0 RW MSIX_Vector31_Address[31:0] MSI-X vector31 message lower address.
0x1F4 31:0 32’h0 RW MSIX_Vector31_Address[63:32] MSI-X vector31 message upper address.
0x1F8 31:0 32’h0 RW MSIX_Vector31_Data[31:0] MSI-X vector31 message data.
0x1FC 31:0 32’h0 RW

MSIX_Vector31_Control[31:0] MSI-X vector31 control.

Bit Position:

31:1: Reserved.

0: Mask. When set to one, this MSI-X vector is not used to generate a message.

0xFE0 31:0 32’h0 RW

Pending_Bit_Array[31:0]

MSI-X Pending Bit Array. There is one bit per vector. Bit 0 corresponds to vector0, etc.