Memory Map - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

There are three distinct register spaces, which are described in this section:

  • Bridge Register Memory Map
  • DMA/Bridge Subsystem for PCIe® Register Memory Map
  • Enhanced Configuration Access Memory Map

In AXI Bridge for PCI Express Gen3 IP, only Bridge Register Memory Map and Enhanced Configuration Access Memory Map are used. In DMA/Bridge Subsystem for PCI Express® (in AXI Bridge mode), all three register spaces are used. These registers are described in more detail in the following section. During reset, all registers return to default values.

In AXI Bridge for PCI Express Gen3 IP, all registers are accessed through the AXI4-Lite Control Interface and are offset from the AXI Base Address assigned to this interface (C_BASEADDR parameter).

In DMA/Bridge Subsystem for PCI Express in AXI Bridge mode, all registers are accessed through the AXI4-Lite Control Interface and are offset from the AXI base address assigned to this interface. C_BASEADDR parameter has been deprecated in this particular IP and the IP is no longer doing address filtering for the AXI4-Lite Control interface. However, if AXI Interconnect IP is used in the design, AXI Crossbar IP within it will do address filtering based on the AXI Address assigned to each interface. The DMA/Bridge Subsystem for PCI Express in AXI Bridge mode uses bit 28 of the address bus to select between each register space:

  • If the AXI4-Lite Slave address bit 28 is set to 0, access is directed to the Bridge Register Memory Map and Enhanced Configuration Access Memory Map.
  • If the AXI4-Lite Slave address bit 28 is set to 1, access is directed to the DMA/Bridge Subsystem for PCIe Register Memory Map.
Note: Registers that are marked as Reserved may appear writable or have a value other than 0. If your application does data compare after the registers are being written, ensure that it ignores the value being returned on the reserved bit position.

Configuration register attributes are defined in the following table.

Table 1. Configuration Register Attribute Definitions
Register Attribute Description
RO Read-Only: Register bits are read-only and cannot be modified by the software.
RW Read-Write: Register bits are read-write and are permitted to be either Set or Cleared by the software to the desired state.
RW1C Write-1-to-clear-status: Register bits indicate status when read. A Set bit indicates a status event which is Cleared by writing a 1b. Writing a 0b to RW1C bits has no effect.
RWC Write-any-to-clear-status: Register bits indicate status when read. Write of any value clears that entire register set.
W1C Non-readable-write-1-to-clear-status: Register returns 0 when read. Writing 1b clears the status for that bit index. Writing a 0b to W1C bits has no effect.
W1S Non-readable-write-1-to-set: Register returns 0 when read. Writing 1b sets the control set for that bit index. Writing a 0b to W1S bits has no effect.