Memory Map Changes - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

In DMA/Bridge Subsystem for PCIe in AXI Bridge mode, the Bridge Memory Map can be accessed through AXI4-Lite Control interface when address bit [28] is set to 1'b0. When address bit [28] is set to 1'b1, interrupt registers in DMA/Bridge Subsystem for PCIe Memory map is accessed.

Table 1. Memory Map Changes
AXI Bridge for PCIe Gen3 Memory Map DMA/Bridge Subsystem for PCIe in AXI Bridge mode New/Changed/Removed
Memory map Interrupt Decode 2 New
Interrupt Decode 2 Mask New