Overview - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The main components that enable XVC-over-PCIe debug are as follows:

  • Host PC XVC-Server application
  • Host PC PCIe-XVC driver
  • XVC-over-PCIe enabled FPGA design

These components are provided as a reference on how to create XVC connectivity for Xilinx FPGA designs. These three components are shown in the following figure and connect to the Vivado Design Suite debug feature through a TCP/IP socket.

Figure 1. XVC-over-PCIe Software and Hardware Components