PCIe Clock Integration - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The PCIe® differential clock input in the system might need to use a differential input buffer (that is instantiated separately) from the Bridge core. The Vivado® IP integrator automatically inserts the appropriate clock buffer.