PCIe Configuration Space Header - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The PCI™ Configuration Space Header is a memory aperture for accessing the core for PCIe configuration space. This area is read-only when configured as an Endpoint. Writes are permitted for some registers when configured as a Root Port. Special access modes can be enabled using the PHY Status/Control register. All reserved or undefined memory-mapped addresses must return zero and writes have no effect.