PCIe VSEC Header (PCIe-XVC-VSEC only) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

This register is used to identify the PCIe-XVC-VSEC when the Debug Bridge IP is in this mode. The fields are defined by PCI-SIG, but the values are specific to the Vendor ID (0x10EE for Xilinx). The PCIe Ext Capability Header register values should be qualified prior to interpreting this register.

Table 1. PCIe XVC VSEC Header Register Description
Bit Location Field Description Initial Value Type
15:0 VSEC ID This field is the ID value that can be used to identify the PCIe-XVC-VSEC and is specific to the Vendor ID (0x10EE for Xilinx). 0x0008 Read Only
19:16 VSEC Rev This field is the Revision ID value that can be used to identify the PCIe-XVC-VSEC revision. 0x0 Read Only
31:20 VSEC Length This field indicates the number of bytes in the entire PCIe-XVC-VSEC structure, including the PCIe Ext Capability Header and PCIe VSEC Header registers. 0x020 Read Only