The Bridge core provides a Xilinx® design constraint (XDC) file for all supported PCIe, Part, and Package permutations. You can find the generated XDC file in the Sources tab of the Vivado® IDE after generating the IP in the Customize IP dialog box.
For design platforms, it might be necessary to manually place and constrain the underlying blocks of the Bridge core. The modules to assign a LOC constraint include:
- Embedded integrated block for PCIe
- GTH transceivers (for each channel)
- PCIe differential clock input
The following subsection describes the example location constraints.