Port Changes - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
Release Date
3.0 English

The following table shows the new port added to the core in the current release.

Table 1. Port Changes
Name Direction Width
common_commands_out O 26 Bits 1
pipe_tx_0_sigs O 84 Bits 2
pipe_tx_1_sigs O 84 Bits 2
pipe_tx_2_sigs O 84 Bits 2
pipe_tx_3_sigs O 84 Bits 2
pipe_tx_4_sigs O 84 Bits 2
pipe_tx_5_sigs O 84 Bits 2
pipe_tx_6_sigs O 84 Bits 2
pipe_tx_7_sigs O 84 Bits 2
gt_dmonfiforeset 3 I (PL_LINK_CAP_MAX_LINK_WIDTH-1):0
gt_dmonitorclk 3 I (PL_LINK_CAP_MAX_LINK_WIDTH-1):0
  1. This signal width has changed to match common_command_in.
  2. This external pipe interface signal width have changed to match pipe_rx_*_sigs.
  3. This signal was added to transceiver debug and status ports interface and is applicable only for UltraScale™ variants.

The following table shows the cfg_ext_if signals which are available when the CFG_EXT_IF parameter is set to true in the AXI Bridge for PCIe Gen3 only.

Table 2. New Ports
Name Direction Width
cfg_ext_function_number O 8 Bits
cfg_ext_read_data I 32 Bits
cfg_ext_read_data_valid I 1 Bit
cfg_ext_read_received O 1 Bit
cfg_ext_register_number O 10 Bits
cfg_ext_write_byte_enable O 4 Bits
cfg_ext_write_data O 32 Bits
cfg_ext_write_received O 1 Bit