Post-Synthesis/Post-Implementation Netlist Simulation - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The DMA/Bridge Subsystem core for UltraScale+™ devices does not support post-synthesis/post-implementation netlist functional simulations. The AXI Bridge for PCIe® core supports post-synthesis/post-implementation netlist functional simulations. However, some configurations do not support this feature in this release. See the following table for the configuration support of netlist functional simulations.

Post-synthesis/implementation netlist timing simulations are not supported for any of the configurations in this release.

Table 1. Configuration Support for Functional Simulation
Configuration Verilog VHDL PIPE Mode Option/External PIPE Interface Shared Logic in Core Shared Logic in Example Design
Endpoint Yes N/A No N/A