Product Specification - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

The Register block contains registers used in the Bridge core for dynamically mapping the AXI4 memory mapped (MM) address range provided using the AXIBAR parameters to an address for PCIe® range.

The slave bridge provides termination of memory-mapped AXI4 transactions from an AXI master device (such as a processor). The slave bridge provides a way to translate addresses that are mapped within the AXI4 memory mapped address domain to the domain addresses for PCIe. Write transactions to the Slave Bridge are converted into one or more MemWr TLPs, depending on the configured Max Payload Size setting, which are passed to the integrated block for PCI Express. The slave bridge in AXI Bridge for PCI Express Gen3 core can support up to eight active AXI4 Write requests. The slave bridge in the DMA/Bridge Subsystem for PCIe in AXI Bridge mode core can support up to 32 active AXI4 Write requests. When a remote AXI master initiates a read transaction to the slave bridge, the read address and qualifiers are captured and a MemRd request TLP is passed to the core and a completion timeout timer is started. Completions received through the core are correlated with pending read requests and read data is returned to the AXI master. The slave bridge in AXI Bridge for PCI Express Gen3 core can support up to eight active AXI4 Read requests with pending completions. The slave bridge in the DMA/Bridge Subsystem for PCIe in AXI Bridge mode core can support up to 32 active AXI4 Read requests with pending completions.

The master bridge processes both PCIe MemWr and MemRd request TLPs received from the Integrated Block for PCI Express and provides a means to translate addresses that are mapped within the address for PCIe domain to the memory mapped AXI4 address domain. Each PCIe MemWr request TLP header is used to create an address and qualifiers for the memory mapped AXI4 bus and the associated write data is passed to the addressed memory mapped AXI4 Slave. The Master Bridge in AXI Bridge for PCI Express Gen3 core can support up to eight active PCIe MemWr request TLPs. The Master Bridge in the DMA/Bridge Subsystem for PCIe in AXI Bridge mode core can support up to 32 active PCIe MemWr request TLPs. PCIe MemWr request TLPs support is as follows:

  • 4 for 64-bit AXI data width
  • 8 for 128-bit AXI data width
  • 16 for 256-bit AXI data width
  • 32 for 512-bit AXI data width

Each PCIe MemRd request TLP header is used to create an address and qualifiers for the memory-mapped AXI4 bus. Read data is collected from the addressed memory mapped AXI4 slave and used to generate completion TLPs which are then passed to the integrated block for PCI Express. The Master Bridge in AXI Bridge for PCI Express Gen3 core can support up to eight active PCIe MemRd request TLPs with pending completions. The Master Bridge in the DMA/Bridge Subsystem for PCIe core in AXI Bridge mode can support up to 32 active PCIe MemRd request TLPs with pending completions for improved AXI4 pipelining performance.

The instantiated AXI4-Stream Enhanced PCIe block contains submodules including the Requester/Completer interfaces to the AXI bridge and the Register block. The Register block contains the status, control, interrupt registers, and the AXI4-Lite interface.