Receive CCIX Core Interface (512-Bit) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2022-11-16
Version
3.0 English

The RX CCIX interface contains the ports through which the core receives CCIX data from the user application. The following table defines the ports in the 512-bit receive CCIX interface.

Table 1. 512-Bit Receive CCIX Interface Port Descriptions
Port Direction Width Description
m_axis_ccix_rx_tdata Output 512 Transmits data from core to CCIX application.
m_axis_ccix_rx_tuser Output 100 This set of signals contains sideband information on TLP being transferred. These signals are valid when m_axis_ccix_rx_tvalid is High. The individual signals are defined in the following table.
m_axis_ccix_rx_tvalid Output 1 The core asserts this signal whenever it presents valid data on m_axis_ccix_rx_tdata.
ccix_rx_credit_gnt Input 1

This signal is asserted by the user application to release credits to the core. After the VC1 link becomes active, the user application first release all available credits to the core, and then it releases credits as available. The core transmits valid data when there are credits available.

Note: The core can drop valid between packets if there are no available credits.

ccix_rx_credit_rtn Output 1 The core asserts this signal to return the credits to CCIX application when the CCIX link goes to the deactivate state.
ccix_rx_active_req Output 1 This signal is asserted by the core to come out of deactive(stop) state and into active state. This signal needs to remain High as long as the core requires the link to be in active state.
ccix_rx_active_ack Input 1 The CCIX application asserts this signal in response to the ccix_rx_active_req from the core when the application is ready to accept TLP packets.
ccix_rx_deact_hint Input 1 The CCIX application asserts this signal when the application goes through a link reset. The core must use this signal to return the credits and move to link deactive state.
Table 2. Sideband Signals in s_axis_ccix_rx_tuser (512-Bit Interface)
Bit Index Name Width Description
3:0 is_sop[3:0] 4

Signals the start of a TLP in this beat. The encoding is as follows:

  • 0000: No new TLP starting in this beat.
  • 0001: A single new TLP starts in this beat. The start position is indicated by is_sop0_ptr.
  • 0011: Two new TLPs are starting in this beat.
    • is_sop0_ptr provides the start position of the first TLP.
    • is_sop1_ptr provides the start position of the second TLP.
  • 0111: Three new TLPs are starting in this beat.
    • is_sop0_ptr provides the start position of the first TLP.
    • is_sop1_ptr provides the start position of the second TLP.
    • is_sop2_ptr provides the start position of the third TLP.
  • 1111: Two new TLPs are starting in this beat.
    • is_sop0_ptr provides the start position of the first TLP.
    • is_sop1_ptr provides the start position of the second TLP.
    • is_sop2_ptr provides the start position of the third TLP.
    • is_sop3_ptr provides the start position of the forth TLP.
  • All other values: Reserved.
5:4 is_sop0_ptr[1:0] 2

Indicates the position of the first byte of the first TLP starting in this beat:

  • 00: Byte 0
  • 01: Byte 16
  • 10: Byte 32
  • 11: Byte 48
7:6 is_sop1_ptr[1:0] 2

Indicates the position of the first byte of the second TLP starting in this beat:

  • 00: Reserved
  • 01: Byte 16
  • 10: Byte 32
  • 11: Byte 48
9:8 is_sop2_ptr[1:0] 2

Indicates the position of the first byte of the second TLP starting in this beat:

  • 00: Reserved
  • 01: Reserved
  • 10: Byte 32
  • 11: Byte 48
11:10 is_sop3_ptr[1:0] 2

Indicates the position of the first byte of the second TLP starting in this beat:

  • 00: Reserved
  • 01: Reserved
  • 10: Reserved
  • 11: Byte 48
15:12 is_eop[3:0] 4

Signals that a TLP is ending in this beat. These outputs are set in the final beat of a TLP. The encoding are as follows:

  • 0000: No TLPs ending in this beat.
  • 0001: A single TLP is ending in this beat. is_eop0_ptr[3:0] provides the offset of the last Dword of this TLP.
  • 0011: Two TLPs are ending in this beat.
    • is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP.
    • is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP.
  • 0111: Two TLPs are ending in this beat.
    • is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP.
    • is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP.
    • is_eop2_ptr[3:0] provides the offset of the last Dword of the third TLP.
  • 1111: Two TLPs are ending in this beat.
    • is_eop0_ptr[3:0] provides the offset of the last Dword of the first TLP.
    • is_eop1_ptr[3:0] provides the offset of the last Dword of the second TLP.
    • is_eop2_ptr[3:0] provides the offset of the last Dword of the third TLP.
    • is_eop3_ptr[3:0] provides the offset of the last Dword of the fourth TLP.
  • All other values: Reserved.
19:16 discontinue[3:0] 4

This signal can be asserted by the core during a transfer if it has detected an error in the data being transferred and needs to abort the packet. The user logic nullifies the corresponding TLP on the link to avoid data corruption.

The core asserts this signal in any beat of a TLP. It can either choose to terminate the packet prematurely in the cycle where the error was signaled, or continue until all bytes of the payload are delivered to the core.

The discontinue signal can be asserted only when s_axis_ccix_rx_tvalid is High.

23:20 is_eop0_ptr[3:0] 4 Indicates the offset of the last Dword of the first TLP ending in this beat. This output is valid when is_eop[0] is asserted.
27:24 is_eop1_ptr[3:0] 4 Indicates the offset of the last Dword of the second TLP ending in this beat. This output is valid when is_eop[1] is asserted.
31:28 is_eop2_ptr[3:0] 4 Indicates the offset of the last Dword of the third TLP ending in this beat. This output is valid when is_eop[2] is asserted.
35:32 is_eop3_ptr[3:0] 4 Indicates the offset of the last Dword of the fourth TLP ending in this beat. This output is valid when is_eop[3] is asserted.
99:36 data_parity[63:0] 64

Odd parity for the 512-bit data. The core sets bit i of this bus to the odd parity computed for byte i of s_axis_ccix_rx_tdata.

On detection of a parity error, the user application can nullifies the corresponding TLP on the link and treat it as an Uncorrectable Internal Error.