Reference Clock for PCIe Frequency Value

Reference Clock for PCIe Frequency Value - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID

PG194

Release Date

2023-11-24

Version

3.0 English

The reference clock input used by the serial transceiver for PCI® must be 100 MHz, 125 MHz, or 250 MHz. Note that the reference clock is refclk in AMD Virtex™ 7 devices, and sys_clk_gt in AMD UltraScale™ and AMD UltraScale+™ devices. The REF_CLK_FREQ parameter is used to set this value, as defined in Bridge Parameters. The reference clock input must be fed in from a clock source that is external to the chip.